The multi-phase oscillator plays an important role in many data communication applications. There are many proposed methods of implementing a multi-phase oscillator. For example, a ring oscillator is an oscillator containing an odd-number of inverters in cascade. Because of the odd-numbered cascade stages, the outputs of the inverters will oscillate between high and low. However, a conventional ring oscillator suffers from the disadvantages that only odd-number of multi-phase signals can be generated with this structure. Another disadvantage is that the maximum attainable frequency decreases as the number of the stages of inverters used in the ring decrease.
U.S. Pat. No. 5,592,126 disclosed a multi-phase output oscillator, including a number of serially coupled oscillators organized in a loop, with each oscillator further including a plurality of interconnected invertors. The disclosed structure can generate an even-number of multi-phase signals. U.S. Pat. No. 6,870,431 disclosed an oscillator having multi-phase complementary outputs, including a first plurality of single-ended amplifiers connected in series to form an input and an output, and a second plurality of single-ended amplifiers connected in series to form an input and an output. The two pluralities of cascade amplifiers are further interconnected with feedback paths and locking circuit to generate multi-phase complimentary signals.
Another widely used method to generate multi-phase clock signals is to use interpolation, also called phase-blending, of a plurality of input signals. FIG. 1 shows a schematic view of a conventional single-stage phase-blender circuit with input signal ΦA, ΦB and output signals ΦA, ΦB, ΦAB, where ΦAB is a signal generated by the interpolation of signals ΦA, ΦB. For example, IEEE Journal of Solid-State Circuits, vol. 34, No. 5 (May 1999) disclosed a portable digital DLL for high speed CMOS interface circuits. However, this interpolation approach usually has the disadvantage of imprecise interpolated signal in terms of phase. This is because the input signals are full swing signals, from which a signal with precise phase between the two input signals is difficult to obtain.
One common approach to overcoming the above imprecise phase problem is to increase the loading at the input, such as by adding capacitors, so that the input signals become non-full swing signals. This will improve the phase precision in the interpolated signals. For example, IEEE Journal of Solid-State Circuits, vol. 35, No. 11 (November 2000) disclosed a 1.3-cycle lock time, non-PLL/DLL clock multiplier based on direct clock cycle interpolation for “clock on demand”. However, this approach has the disadvantage of unstable and shifting electrical characteristic due to the addition of capacitors in the manufacturing process.
It is imperative to provide a multi-phase oscillator that is easy to manufacture, and yet able to provide precise and stable phase interpolation to generate multi-phase signals for various data communication applications.